Embedded system design today is at an interesting kairos. The microcontroller-based designs have enormously benefited by the arrival of the system on chips (SoC) devices. On the one hand, the whole system, which earlier took several components and used up significant board real-estate, are now squeezed in tiny packages. On the other hand, time to market and product life cycle times have exponentially reduced. Product managers now need a different strategy and face a different set of challenges with SoCs. The software development cycle now need boards to be available right at the start of the project. Embedded system designers have almost no time to ramp-up on upcoming devices, which are very compelling to use due to lower cost, smaller size, and/or lower energy offerings.
This transition to faster design cycle workflow has a legacy of using vendor recommended reference design boards. Reference board enables software development to start right away. Meanwhile, hardware developers are working to make board prototype design with all product features needed as per target product specification. This challenge puts lots of pressure on hardware designers, as there is no scope for any design iteration. More-over bread-boarding is almost impossible for complex interface/components that are being used to de-risk design errors.
Extra time and effort is needed to setup stopgap arrangement using reference design board to aid early start of software development. This involves parallel effort of designing temporary daughter board with actual peripheral devices that will be used in final product (in most of the cases). Hardware/Board simulation needs extra stopgap arrangement too; one for the reference design and its models, and other one with final design that needs it own simulation setup. In most cases, the next design will use a different SoC, the knowledge base and good understanding that engineers acquired goes redundant. This takes away the fun and ease designing boards. Engineers always wish for easy design flow that does not have these intermediate steps or if one could reuse of design platform/tools for next project.
Semiconductor vendors have been putting huge resource in developing reference designs. These reference design board covers typical use cases only. In many cases they also end up offering multiple reference design to suit different end customer product development needs. Semiconductor vendors many case also provides system builder tools to help speed up software and system development. These tools in most case have to support earlier family of SoC and current part offerings. Supporting multiple reference designs and different family of devices in many case, break the tool design. This also adds complexity and testing effort while vendors ensure timely release of updated tool along with reference design boards.
Meanwhile, fortunately there has been advancement in design tools as well. Artificial intelligence and expert systems practitioners have developed new efficient algorithms and simplified flow to abstract complex design. This has been a good leverage to ease up SoC based embedded systems design effort and time. Circuit Tree is one such new and innovative tool.
Circuit Tree tool provides a unified platform to design SoC based embedded system design in very short time. Hardware designers can now complete schematic design in very short time of freezing board specification. In three simple steps engineers can now generate board schematic.
Circuit tree tool provides options to interconnect various peripherals and the SoC, choose required form factors to create a highly customized board design that meets product specification. Circuit tree also provides all collaterals to take these complex schematic to layout, these includes layout and routing guidelines and BOM (with popular component source). Designs generated from circuit tree are also free of design mistakes that may crop due to manual and time consuming schematic entry. Circuit tree flow can potentially eliminate step/s of using reference design, because the schematic design is almost instantaneous and reliable.
In three easy steps Circuit Tree can help engineers with schematic design. Circuit Tree provides a convenient web based User Interface (UI) with a drag and drop canvas that supports very wide range components to choose from. In the first step, user needs to choose SoC device central to their design – from over 12 popular ARM based SoC families currently supported by the tool. Circuit Tree supports SoCs from popular vendors including Atmel, Intel, NXP, TI, ST Micro and SI Labs. Circuit Tree will soon support SoC from Nvida, Qualcom and Mediatek. After this, users can choose components that define interfaces that are required for their products. Circuit Tree supports all interfaces supported by the selected SoC, be it USB, PCIe, SPI, SD, CAN, UART, Display drivers, Memory (DDR/Flash), standard PHY or Transceiver (MII/GMII/CAN/ULPI), JTAG/SWD, etc. Next, the user configures the power management details, like IO voltage selection, power up sequences, etc.
Users can then modify/update reset and clock configuration as per their design requirements. After adding other requirements like custom IO, sensors, GPIOs, linear analog components like ADC/DAC, level translators, RF modules and connectors as needed by the design into the canvas. Users then define the board form-factor and interconnects. Circuit Tree supports most industry standard form-factors including PCIe, XMC, PMC, ATX or any custom form-factor that user needs. Finally users defines interconnects between all the components on the canvas to compete the schematic definition.
In step two, Circuit Tree tool runs its AI engine to optimizes the SoC pin mux options, creates clock and reset tree abstraction as configured. Circuit Tree engine uses this comprehensive abstraction and along with its internal detailed knowledge base that covers diligently all properties described as per vendor data sheet, brews the final schematic. This schematic is visible to users in muti-page UI for review (and iterate between different configurations if needed) and freeze. Once the schematic design is finalized users can export the schematic to take into any of the popular CAD tools.
In the final Step, Circuit Tree provides all necessary output collaterals needed to take schematic to layout tool. Circuit Tree generates Bill of materials (BOM) that supports from choice of components vendors like Digikey, Moser, etc. Circuit Tree also generates netlist, layout guidelines that include placement and routing requirements that is optimized for form factor that user has defined. Users can directly take the output from Circuit Tree to standard PCB Layout CAD tool. Currently Circuit Tree supports export to Cadence Allegro, Mentor Pads, Altim or Eagle.
Engineers can then use standard PCB layout design flow to compete PC board design for exact form factors required by the product specification. This reduces difficulties in design cycle where one ends up buying expensive reference design boards/platforms that semiconductor vendor recommend, which is built to contain all generic interfaces.
Since Circuit tree support SoC design from all major/popular vendors, it enables product teams to ease up migration of design from one SoC to another quickly, if such a need arise.
Currently, Circuit Tree in beta release phase and free trials are still open. Please explore this new automated schematic design flow that will enable you to quickly turn around your product design in ways that you would have not seen so far. Circuit Tree has excellent support team to help you through the evaluation process.
Short Introduction to Circuit tree
Circuit Tree is an online EDA application having the intelligence of a hardware engineer to create embedded hardware designs. It features more than 1000+ processors and controllers along with extended hardware peripheral library.
Here is an introduction video to Circuit Tree:
To start building designs click on link Link.