Peripherals and Misc Blocks:

  • Peripherals and Misc Blocks
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  • 1. DDR3/L memory library
     

    a. Supports 8 Bit/16 Bit memories for a bus size of 16 bit to 64 wide bit.
    b. Added VTT termination support.
    c. Can support multiple DDr3 IP of processors.
    d. Additional features:
    i. Memories selected based on datarate, cas latency, single/dual die option.
    ii. Takes care of DQS and Data group connection to various memory type.
    iii.Provision to allow processor connections routed to a connector in place of memory.
    e. Planned development
    i. DIMM/SODIMM support
    ii. ECC support
    iii. Dual Die memory support.

  • 2. Parallel Memory library
     

    a. Asynchronous Nor [16 Bit] -Support various memory sizes
    b. Synchronous Nor [16 Bit] -Support various memory sizes
    c. Nand Flash [8 bit] -Support various memory sizes
    d. Async Sram [16 Bit] -Support various memory sizes
    e. Additional features:
    i. Select Based on memory density, manufacturer etc.
    ii. Supports Non Multiplexed memories at present.
    iii. Provision to allow processor connections routed to a connector in place of memory.
    f. Planned development
    i. 8 Bit mode support for Async NOR, Sync Nor, Async NOR

  • 3. Serial Memory Library
     

    a. QSPI -Various memory sizes
    b. SPI -Various memory sizes
    c. I2c-Various memory sizes
    d. Additional features:
    i. Select Based on memory density, manufacturer
    ii. Select addresses needed for each i2c device
    iii. Route the QSPI,SPI, i2c processor pin connections to any connector
    e. Planned development
    i. Support to add a i2c bus to multiple devices
    ii. Support to connect multiple spi devices on one spi bus if multiple chip select exists.

  • 4. Ethernet Library
     

    a. Transceivers
    i. SGMII
    ii. GMII
    iii. RGMII
    iv. RMII
    v. MII
    b. Additional features:
    i. Auto selection of transceivers and option to change the transceiver to one of the transceivers from menu option. Auto routing for MDC/MDIO signals for all the transceivers.
    ii. Ethernet phy connections are routed to the integrated magnetics.
    iii. Option to change management bus address, type of clocks, txdelays, rxdelays of the selected transceivers. Circuit tree will automatically change the configurations pins as needed.
    iv. Option to route the selected bus connection to a connector.
    c. Planned development
    i. Provide option to use separate magnetics and RJ45 connector for lower cost.
    ii. Allow connections from magnetics to be routed to a connector.
    iii. Allow Power over Ethernet option

  • 5. USB Library
     

    a. Select ULPI Transceivers from various manufacturers
    b. USB2.0 and USB3.0 ports from processor
    i. Select USB type from requirement editor OTG/HOST/DEVICE. Connectors, esd protection diodes, usb power etc are automatically chosen.
    ii. Multiple peripheral support.
    iii. Route connections to a connector
    c. Planned development
    i. Allow differential connections to be routed to a connector.
    ii. Add support for USB Type C.

  • 6. Display library
     

    a. Graphics LCD
    b. OLED LCD
    c. TFT LCD
    d. HDMI differential signals
    e. LVDS connection using display Bus
    f. HDMI output Using display bus
    g. DVI output using display bus
    h. Additional features:
    i. Option to select Component configuration
    ii. Route connections to a connector.
    i. Planned development
    i. Allow wider display ports using display bus.
    ii. Add additional components in the library

  • 7. Wireless Library
     

    a. WIFI modules
    b. Bluetooth module
    c. NFC module
    d. Radio 2.4Ghz module
    e. Zigbee module
    f. GPS module
    g. Additional features:
    i. Component configuration
    h. Planned development work
    i. Allow RF device design.
    ii. Add additional components in the library

  • 8. Sensor Library
     

    a. Temperature
    b. Accelerometer
    c. Humidity
    d. Compass
    e. Pressure
    f. Gyroscope
    g. RTC

  • 9. UART library
     

    a. RS232 Phy transceivers
    b. UART to USB converter transceivers
    b. Additional features
    i. Option to route the signals to DB9 or a 2x5 header
    ii. Option to route any custom connector.
    c. Planned development
    i. RS485
    ii. Add Multiple components to the library.

  • 10. Jtag Library
     

    a. ARM Jtag 2x10 header
    b. ARM Jtag 2x5 header
    c. ARM SWI 2x5 header
    d. ARM SWI 2x10 header
    e. Additional features:
    i. Option to route any custom connector.
    ii. The reset from the Jtag connector is automatically wired to reset the complete board.

  • 11. PCIe library
     

    a. Mini PCIe slot
    b. PCie x1, x4 and x8
    c. Additional features:
    i. Option to route any custom connector.

  • 12. Sata library
     

    a. Sata connector without power pins.
    b. Additional features:
    i. Option to route any custom connector.

  • 13. SD library
     

    a. SDHC connector
    b. Micro SD card connector.
    b. Emmc Memory
    Additional features:
    i. Option to route any custom connector

  • 14. Audio library
     

    a. Select any of the Audio transceivers
    b. Additional features:
    i. Option to select audio part
    ii. Option to select features.
    iii. Option to route any custom connector

  • 15. CAN library
     

    a. Select any of the CAN transceivers
    b. The can transceiver connections are routed to a db9 connector by default.
    c. Additional features:
    i. Option to select CAN part
    ii. Option to select features for a transceiver
    iii. Option to route any custom connector

  • 16. Camera Library
     

    a. Select Camera modules
    b. Additional features:
    i. Option to route any custom connector
    ii. Accepts reset or provides reset to the connector from board reset circuit.
    ii. Automatically finds clock requirements of the part and assigns the required clock to the module.
    c. Option to route any custom connector

  • 17. Connector
     

    a. With this option single/multiple processor bus pin signals can be routed to a single/multiple connectors. A connector with number of rows and column is specified by the user. A reference designator is allocated and then the bus signals can be easily routed.
    b. Accepts reset or provides reset to the connector from board reset circuit.
    c. Planned development
    i. Option to define multiple power input/output requirement
    ii. Option to define multiple clock input/output requirement.

  • 18. GPIO/ADC/DAC Library
     

    a. Number of GPIO’s, ADC’s and DAC’s needed can be assigned through processor pin mux to a connector for the custom development.
    b. Additional features:
    i. Ground is added in between signals routed to the connector.
    ii. The application will also automatically select gpio pins for peripherals. For instance gpio for the usb power switch , interrupt pin etc.
    c. Planned development
    i. Ability to accept analog input and generate a analog front end circuit for it.

  • 19. Button/LED Library
     

    a. Power on Button
    b. Board reset button
    c. Power good Green LED
    d. Power failure Red LED
    e. Reset Asserted Red LED
    f. Reset De-asserted Green LED

  • 20. Board Form factor
     

    a. PCie x1, x4, x8 endpoint
    b. Mini PCie Form factor
    c. XMC form factor
    d. PMC form factor
    e. ATX standard
    f. Custom
    g. Additional features:
    i. For all form factors except Custom:
    1. Accept multiple power, clock and reset inputs as defined in standard.
    ii. For custom form factor
    1. Accept power through a main power connector or through custom connectors.

  • 21. Temperature
     

    a. Commercial
    b. Industrial
    c. Extended
    d. Planned development
    i. Parts are selected based on the user temperature requirement.