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Reference designs are already provided by semiconductor companies. How can circuit tree help?

The reference designs provided by semiconductor companies are already proven and are used as a reference for most of the design. However the reference designs cater to a fixed functionality only. Using a existing design and modifying it is not always straightforward. Try adding /changing components in the design to see the effort it takes.

With circuit tree you get the benefit of reduced time to market and flexibility to change design on the fly and generating it with a reduced time to design.

How can the application help a semiconductor company?

There are several benefits:
1. We can easily integrate with documentation team and have models created right at silicon launch.
2. Your Customers can quickly create designs as per there requirement with circuit tree with less support work for the application team.
3. It benefits your board team as they can use the circuit tree platform to create design quickly by deleting a old processor and adding the new processor model.
4. Different form factor boards can be easily created with circuit tree.

What are the type of clock circuits generated by the application?

The application can design a clock circuit for an embedded design using these different type of components

  1. Single ended clocks
  2. Clock crystals
  3. Differential clocks
  4. Single ended Clock buffers
  5. Differential clocks buffers
  6. Custom circuit clock generators (Ex. PCIe)
  7. Component generated clocks.

In beta release users will have an option to optimize and create dynamic circuits with options to changes how the clocks should be connected on board.

What are the limitations of the circuit tree application?

Currently we are not offering  design solutions for:

  1. RF design are not currently supported by the tool.
  2. Analog filters etc are not currently supported by the tool.
  3. Programmable logic such as FPGA and CPLD can be added only with a xml file in circuit tree. This feature is not supported in the tool yet.
  4. The exported EDA files can have grid issues which can cause connections to be broken. We are working to resolve them.

 

Can the application also do timing calculation and Pre-Signal integrity analysis?

Timing calculations : Yes.  In the beta version of the application the layout help document contains the the various signal and clock routing constraints for peripheral connections. For reset, power generation and distribution timing calculations are done to ensure that it meets the circuit requirement. It does not generate separate timing information in any document.

Pre-Signal integrity information: No. It is highly recommended that the pre signal integrity analysis be performed on the design generated by application.